Despite the radical shift in signaling, the specification maintains strict backward compatibility. Legacy PCIe 1.0 through 5.0 devices will work in PCIe 6.0 slots, protecting existing hardware investments.
For the first time in PCIe history, the specification introduces a lightweight Forward Error Correction (FEC) mechanism alongside the standard CRC (Cyclic Redundancy Check). Because PAM4 signaling is more susceptible to noise, relying solely on CRC would result in too many retries, killing performance. The addition of FEC ensures data integrity while maintaining the ultra-low latency requirements that PCIe is known for.
If you have obtained the PCI Express Base Specification Revision 6.0 PDF (either via membership or an authorized preview), prioritize these sections:
| Section | Topic | Why It's Important | | :--- | :--- | :--- | | Chapter 4 | Physical Layer (PAM4) | Details voltage levels, jitter tolerance, and equalization. | | Chapter 6 | Link Layer (FLIT) | Defines FLIT packing, sequence numbers, and ACK/NAK protocols. | | Chapter 8 | Logical PHY (FEC) | Explains the Reed-Solomon code implementation for error correction. | | Appendix A | LTSSM Addenda | New state transitions for mixed PAM4/NRZ environments. | | Appendix G | Compliance Test Spec | Defines what oscillators and probing points are needed for validation. |
Because PAM4 is inherently noisier, PCIe 6.0 introduces low-latency FEC as a mandatory feature.
If you are downloading the PCI Express Base Specification Revision 6.0 PDF to understand reliability, focus on Chapter 8 (Physical Layer Logical Sub-block) .
Network interface cards (NICs) at 800GbE require roughly 100 GB/s of PCIe bandwidth. PCIe 6.0 x16 comfortably handles this, paving the way for 1.6Tb Ethernet in the future.