Ironically, while PCIe 5.0 doubles bandwidth, it can also double power consumption. The new M.2 specification mandates support for:
While Rev 5.0 V1.0 is the current standard, the industry is already discussing M.2 for PCIe 6.0. However, the 1.0 version of the Gen5 spec includes forward-thinking notes: pci express m.2 specification revision 5.0 version 1.0 pdf
Nevertheless, for the next 3-5 years, PCIe 5.0 M.2 Rev 5.0 V1.0 will dominate high-performance storage. Ironically, while PCIe 5
New Junction Temperature Reporting via SMBus (using M.2’s existing 3.3Vaux and SMBus pins) is recommended. Module designers must report: While Rev 5
This allows the host to throttle PCIe link speed or issue L1 substate commands before thermal throttling impacts signal integrity.
A critical technical nuance in the PCIe 5.0 era—and specifically addressed in the M.2 5.0 documentation—is the modulation scheme.
Unlike the recently released PCIe 6.0 specification, which transitions to PAM4 (Pulse Amplitude Modulation 4-level) signaling to achieve 64 GT/s, PCIe 5.0 retains NRZ (Non-Return-to-Zero) signaling.